Fujitsu Labs Can Form Graphene Transistors on Silicon Wafers
Fujitsu Laboratories also developed a process for forming transistors that use graphene as the channel material, as outlined in the picture. This process is independent of wafer size, so it can be applied to large-scale substrates.
1. First, an iron catalyst is formed into the desired channel shape, using a conventional photolithographic process.
2. Graphene is then formed on the iron layer via CVD.
3. Source and drain electrodes of titanium-gold film are formed at both ends of the graphene, thereby “fixing” the graphene.
4. Next, just the iron catalyst is removed using acid, leaving the graphene suspended between the source and drain electrodes, with the graphene “bridged” between the electrodes.
5. Using atomic-layer deposition (ALD), a method for forming thin films, a layer of hafnium dioxide (HfO2) is grown on top of the graphene to stabilize the graphene.
6. Finally, a gate electrode is formed on top of the graphene and through the HfO2, resulting in the formation of a graphene transistor.
